This disclosure relates to memory address translation.
Memory address translation apparatus, such as management units (MMUs), attend to the translation of virtual memory addresses into physical memory addresses.
A data processing apparatus typically provides each running program with access to a virtual address space defined by virtual memory addresses. Each program sees its own virtual address space which contains instructions and data for use by that program. Amongst other established advantages, the use of virtual addressing allows the operating system to control memory access by inhibiting one program from accessing or corrupting information used by another program.
When an access is required to a virtual memory address, it is first necessary to translate the virtual memory address to a physical memory address so that the required information can be obtained from or written to the physical memory or a physical memory cache.
A cache sometimes known as a translation lookaside buffer (TLB) may be used as part of the address translation process. The TLB stores recently or commonly used translations between virtual and physical memory addresses. So, as a first step in an address translation process, the TLB is consulted to detect whether the TLB already contains the required address translation. If not, then a more involved translation process may be used, for example involving consulting so-called page tables holding address translation information, typically resulting in the TLB being populated with the required translation.